Graph-based physical synthesis provides tight correlation to final timing

Find Bugs Quickly
The Synplify Premier software provides a rapid method of finding functional errors in FPGA designs by providing simulator-like visibility into live-running hardware. The methodology is based on technology found in the Identify® RTL Debugger - the first and only tool that allows designers to instrument and debug directly in RTL source code. Synplify Premier’s debugger technology provides designers with:

• ability to add probes and trigger conditions in familiar RTL source code
• ability to see sequence of captured results annotated in context to the RTL code
• fast, incremental debug flow ability to bypass time-consuming iterations through place & route

DSP Friendly Synthesis
As DSP functionality within FPGAs continues to rise, the Synplify Premier software’s DSP-aware mapping technology takes full advantage of the dedicated DSP structures and memories built in to today’s modern FPGAs. The Synplify Premier tool’s DSP aware synthesis provides:

• DSP-friendly synthesis algorithms
• RTL DSP functions automatically mapped into vendors’ DSP hardware
• tight integration with Synopsys' Synplify DSP software

ASIC Verification using Single FPGA-based Prototypes
As a part of Synopsys' Confirma ASIC/ASSP Verification Platform, the Synplify Premier solution offers the most comprehensive system for implementing single FPGA-based ASIC prototypes. Synplify Premier’s ASIC prototyping features offer:

• built-in gated clock conversion
• Synopsys DesignWare® Support
• tight integration with Synopsys' HAPS™ High-performance ASIC Prototyping System

	HAPS-A31 prototyping board
	HAPS-51 Prototyping board

System-Level Implementation and IP Integration
The System Designer™ capability, a key component of the ReadyIP program, allows users to select, configure and assemble internal and third-party IP delivered in the IP-XACT format, integrate that IP and then easily implement it into a variety of FPGA vendor devices. The System Designer capability offers:

• the use of Spirit IP-XACT Compliant IP
• the ability to Configure And Interconnect IP For System
• easy Drag & Drop Connectivity
• easy Reuse Of In-house, Proprietary IP
• Eclipse-based format

Access To Third Party IP for Evaluation and Download
The ReadyIP Initiative is a program that simplifies the access, evaluation, and use of IP for FPGA-based system design. It is an encrypted design methodology for FPGA implementation that allows users to incorporate and easily integrate IP from several third-party vendors within their designs using Synopsys’ industry-standard synthesis environments, the Synplify Pro® and/or Synplify® Premier solutions. The ReadyIP initiative offers:

• standards-based, accessible and secure IP distribution environment
• easy-to-Use IP evaluation mechanism
• IP configuration and assembly integrated into Synopsys' synthesis products
• partnership with leading IP vendors

Digital Clock Managers (DCMs) provide advanced clocking capabilities to Spartan™-3 FPGA

applications. DCMs optionally multiply or divide the incoming clock frequency to synthesize a

new clock frequency. DCMs also eliminate clock skew, thereby improving system performance.

Similarly, a DCM optionally phase shifts the clock output to delay the incoming clock by a

fraction of the clock period. The DCMs integrate directly with the FPGA’s global low-skew clock distribution network.

Блок управления тактовыми генераторами (Digital Clock Managers (DCMs) обеспечивает расширенные возможности тактовой синхронизации для ПЛИС серии Spartan™-3. Этот блок осуществляет умножение или деление частоты от внешнего тактового генератора для получения требуемой тактовой частоты.

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